Available online
Description
An analysis of the way in which the OPUS computer hardware handles the instruction ADD.
An analysis of the way in which the OPUS computer hardware handles the instruction ADD.
| Module code and title: | TM221, The digital computer |
|---|---|
| Item code: | TM221; 04 |
| First transmission date: | 19-04-1975 |
| Published: | 1975 |
| Rights Statement: | |
| Restrictions on use: | |
| Duration: | 00:24:30 |
| + Show more... | |
| Producer: | Ted Smith |
| Contributors: | Roger Loxton; Steve Matheson |
| Publisher: | BBC Open University |
| Keyword(s): | Data routing; Digital computing; Fetch-execute cycle; Instructions; Micro-program |
| Footage description: | Roger Loxton introduces the programme and reviews the last programme, TM 221/03, with the assistance of a large scale OPUS. He shows us what OPUS looks like with the front panel off. Steve Matheson introduces a functional model of the OPUS computer in the form of an illuminated graphics board. He uses this to represent the different components of OPUS and the data paths that link them. Loxton uses another illuminated graphics board to explain the details of the ADD instruction which is to be analysed. He uses the lights on the large scale OPUS to show how the progress of instructions can be recognised. He runs the ADD instruction firstly by the single shot button, and then by means of an external push button which enables OPUS to operate in the simplest possible way. This demonstrates that the ADD instruction comprises 18 steps, or what is called the fetch execute cycle. Loxton then shows on the illuminated graphics board the goal of the first part of the ADD instruction - the initial steps by which it is transferred to the instruction register. Matheson traces in detail the 4 steps necessary within the computer to achieve this goal. On the graphics board he traces the progress from the main store to the instruction register. Loxton then examines the effects of these steps on the actual numbers held in the computer. He briefly states what the next steps will achieve. Matheson demonstrates the 4 steps whereby the store address register is incremented. He describes the steps in terms of the way in which data is routed from one part of the computer to another. Loxton looks at the effects of these 4 steps on the numbers involved in the fetch execute cycle. He then briefly outlines the final stages of the fetch operation. Matheson shows the 4 steps whereby the computer transfers data from the main store and into one of the central processor unit registers. Loxton then explains the effects of these final steps in the fetch instruction on the numbers involved in the whole fetch execute cycle. Using his particular graphics board, Loxton introduces the start of the execute operation. He explains what takes place during the final six steps. Matheson describes the way these steps are carried out in the computer. He then briefly reviews all eighteen steps, saying why each is necessary. Loxton concludes the programme, stating the implications of what's been learnt. |
| Master spool number: | 6HT/71612 |
| Production number: | 00525_5164 |
| Videofinder number: | 1462 |
| Available to public: | no |
